The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
As the semiconductor industry progresses into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of multilayer (or three dimensional) integrated devices. For example, as device sizes continue to shrink, conventional methods of forming contact holes (or contacts) have led to problems such as non-uniform silicide grain size, excessive contact resistance, leakage issues, etc. As a result, semiconductor device performance may be degraded and defect count may increase. Therefore, while existing methods of fabricating semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.